1. Field of the Invention
The invention relates to a method for fabricating a strained-silicon CMOS transistor.
2. Description of the Prior Art
As semiconductor technology advances and development of integrated circuits continues to revolution, the computing power and storage capacity enjoyed by computers also increases exponentially. As a result, this growth further fuels the expansion of related industries. As predicted by Moores Law, the number of transistors utilized in integrated circuits has doubled every 18 months and semiconductor processes also have advanced from 0.18 micron in 1999, 0.13 micron in 2001, 90 nanometer (0.09 micron) in 2003, to 65 nanometer (0.065 micron) in 2005.
As the semiconductor processes advance, determining methods for increasing the driving current for metal oxide semiconductor (MOS) transistors for fabrication processes under 65 nanometers has become an important topic. Currently, the utilization of high stress films to increase the driving current of MOS transistors is divided into two categories. The first category is that being a poly stressor formed before the formation of nickel silicides. The second category being a contact etch stop layer (CESL) formed after the formation of the nickel silicides.
Please refer to FIGS. 1-6. FIGS. 1-6 are perspective diagrams illustrating a method for fabricating dual contact etch stop layer on a strained-silicon CMOS transistor according to the prior art. As shown in FIG. 1, a semiconductor substrate 100 having an NMOS region 102 and a PMOS region 104 is provided, in which the NMOS region 102 and the PMOS region 104 are divided by a shallow trench isolation 106. Each of the NMOS region 102 and the PMOS region 104 includes a gate structure. The NMOS gate structure includes an NMOS gate 108 and a gate dielectric 114 disposed between the NMOS gate 108 and the semiconductor substrate 100. The PMOS gate structure includes a PMOS gate 110 and a gate dielectric 114 disposed between the PMOS gate 110 and the semiconductor substrate 100. The sidewall of the NMOS gate 108 and the PMOS gate 110 includes a liner 112 composed of silicon dioxide or silicon nitride.
Next, an ion implantation process is performed to form a source/drain region 116 around the NMOS gate 108 and a source/drain region 117 around the PMOS gate 110 and within the semiconductor substrate 100. A rapid thermal annealing process is performed thereafter to utilize a temperature between 900° C. to 1050° C. to active the dopants within the source/drain region 116 and 117 for forming an NMOS transistor 132 in the NMOS region 102 and a PMOS transistor 134 in the PMOS region 104, and repair the lattice structure of the semiconductor substrate 100, which has been damaged during the ion implantation process. Additionally, a lightly doped drain (LDD) 118 and 119 can be formed between the source/drain region 116, 117 and the gate 108, 110.
Next, a metal layer (not shown), such as a nickel layer is sputtered on the surface of the semiconductor substrate 100, and a rapid thermal annealing process is performed to react the metal layer with the NMOS gate 108, the PMOS gate 110, and the source/drain region 116 and 117 to form a plurality of salicide layers 115. It is to be understood that the fabrication of the lightly doped rain, the source/drain extension, and the salicide layer relating to the present invention method is well known by those of average skill in the art and thus not further explained herein.
After the un-reacted metal layer is removed, a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a high tensile stress film 120 over the surface of the salicide layers 115 within the NMOS region 102 and the PMOS region 104. Next, a series of coating, exposure, and development processes are performed to form a patterned photoresist 122 on the NMOS region 102.
As shown in FIG. 3, an etching process is performed to remove the high tensile stress film 120 disposed on the PMOS region 104, thereby leaving a high tensile stress film 120 on the NMOS transistor 132. The patterned photoresist 122 is removed from the NMOS region 102 thereafter.
As shown in FIG. 4, another PECVD process is performed to form a high compressive stress film 124 on the MOS region 102 and the PMOS regions 104. Preferably, the high compressive stress film 124 is disposed on the high tensile stress film 120 in the NMOS region 102 and disposed on the PMOS transistor 134 in the PMOS region 104.
As shown in FIG. 5, a series of coating, exposure, and development processes are performed to form a patterned photoresist 126 on the PMOS region 104. Next, an etching process is performed by using the patterned photoresist 126 as a mask to remove the high compressive stress film 124 disposed on the NMOS region 102. The patterned photoresist 126 disposed on the PMOS region 104 is removed thereafter, thereby leaving a high compressive stress film 124 on the PMOS transistor 134 and a high tensile stress film 120 on the NMOS transistor 132.
As shown in FIG. 6, an inter-layer dielectric 128 is disposed on the high tensile stress film 120 and the high compressive stress film 124. Next, an anisotropic etching process is performed by utilizing a patterned photoresist (not shown) as an etching mask and utilizing the high tensile stress film 120 and the high compressive stress film 124 as a contact etch stop layer to form a plurality of contact holes 130 in the inter-layer dielectric 128. The contact holes 130 are used as a bridge for connecting other electronic devices in the later process.
It should be noted that in the convention art, a patterned photoresist is formed on an active region, and an etching process performed thereafter by using the patterned photoresist as a mask to remove the stress layer disposed on another active region, as shown in FIGS. 2-3. This method removes the stress layer from the transistor rapidly, but also over-etches and damages the salicide layer disposed under the stress layer and ultimately influences the yield for fabricating contact holes in the later process.
Additionally, during the process for etching the high tensile stress film disposed on the NMOS transistor and the high compressive stress film disposed on the PMOS transistor, the definition of the region between the two stress layers is difficult and easily result in an overlapping phenomenon, as shown in FIG. 5, in which one stress layer is stacked on top of another. Typically, if the width of the overlapping region is less than 30 nm, a peeling phenomenon would result after the photoresist is stripped or a wet etching process is performed. If the width of the overlapping region of the two stress layers is greater than 30 nm, the peeling phenomenon is prevented but after a series of back end processes such as photoresist stripping or chemical mechanical polishing are performed, the overlapping region would break and result in defect of the device.